Implementation and Evaluation of an HyperBUS interface

Publicerad: 26 juni 2017

One of the new RAM memory interfaces, named HyperRAM which operates over the HyperBUS protocol opens up for new possibilities in low-cost FPGA systems, in such where external memory is required but
the complexity of DDR RAM wants to be avoided. We aim to make an Open Source interface to communicate with the a HyperRAM.

  • A project in VHDL and FPGAs.
  • The task is to create an interface with a HyperRAM, provided on an carrier board to the Arty FPGA evaluation board, which has multiple FIFO streams accessing the memory.
  • Evaluate so the chip can be used close to maximum throughput, without errors.


Proposal from Emil Fresk, Control Engineering Group, www.ltu.se
Emil Fresk: emil.fresk@ltu.se Room A2571